FIG. 1 is a block diagram illustrating a conventional synchronous burst pipelined SRAM (Static Random Access Memory) device operating in synchronism with an externally applied clock signal. The SRAM device 100 integrates an SRAM core with synchronous peripheral circuitry. The SRAM device 100 has a mode of write operation in which the write data are written into memory cells at least one clock cycle after the addresses and control inputs have been presented.
The prior art memory device 100 can access data in response to both rising and falling edges of an external clock signal CK (or CK#), as well as accessing the rising (or falling) edge of the clock signal. In other words, the device 100 can operate in either one of the single data rate (SDR) and double data rate (DDR) modes of operation. The SDR mode of operation allows a user to read or write a single word on every rising edge of the clock signal CK, and the DDR mode allows a read or write operation in synchronism with both the rising and the falling clock edges of the clock signal CK.
The SRAM device 100 includes a clock buffer 102, an address register 104, a burst address sequence counter 106, a write address register 108, 2.times.1 multiplexers 110, 124a, 124b, 124c, 136 and 138, an address decoder 112, an SDR/DDR output control logic 114, an address comparator 116, logic gates 118 and 150, data input registers 120 and 122, a write register 126, a write driver 128, a memory cell array 130, a sense amplifier circuit 132, an output register 134, an output buffer 140, a data rate register 142, a read/write enable register 144, an output enable register 148, and echo clock buffers 152 and 154.
To the SRAM device 100, a data rate signal SD/DD# indicating the SDR or DDR mode and a burst type signal LBO# indicating a linear or interleaved burst type are externally applied. In SDR mode, write data are registered on the rising of the clock signal CK. In DDR mode, write data are registered on both the rising and falling edges of the clock signal CK. Read data are driven on the rising edge of the clock signal CK in SDR mode and on the rising and falling edges of the clock signal CK in DDR mode. Address signals SA0' and SA1' are advanced in the order indicated by the signal LBO#.
FIG. 2 is a timing diagram of the prior art SRAM device 100 shown in FIG. 1. For purposes of explanation, it is assumed that the prior art SRAM device 100 supports burst lengths of 1, 2 and 4, and that the memory device has a two stage delay feature. As can be seen in FIG. 2, when a command DW4 representing a DDR burst write operation with burst length of 4 (hereinafter abbreviated as "DW4 operation") is externally issued in cycle C1 of the external clock signal CK, an external address A0.sub.-- b as an initial burst address is presented on the rising edge of the external clock signal CK. Since the SRAM device is the late write type, in next cycle C2 of the clock signal CK (i.e., a burst write continue cycle without any external address input), a pair of write data W0b and W0a are sequentially inputted on the rising edge and the falling edge of the clock signal CK, respectively.
During cycle C3 of the clock signal CK, in which a command DW2 representing a DDR burst write operation with burst length of 2 (hereinafter abbreviated as "DW2 operation") is issued, two subsequent write data W0d and W0c corresponding to the command DW4 are also inputted in synchronism with the rising and falling edges of the clock signal CK, respectively. The input sequence of the write data W0d, W0c, W0a and W0b, is determined by the external address A0.sub.-- b and the selected burst mode (i.e., either interleaved or linear burst mode).
Due to the 2 stage delay write feature of the SRAM device, an internal address WA0.sub.-- ab for the write data W0b and W0a is generated in cycle C3, and so the data W0b and W0a are written into memory cells selected by decoding the address W0.sub.-- ba. The reference symbol WA0.sub.-- ab of the burst write address for the write data W0b and W0a represents that both of the data W0b and W0a having been serially inputted are written into the selected memory cells in parallel.
In cycle C4, a pair of write data W1a and W1b are inputted at the rising and falling edges of the clock signal CK in response to the command DW2 issued in cycle C3. However, when a command DR4 representing a DDR burst read operation of burst length 4 (hereinafter abbreviated as "DR4 operation") is given in cycle C4, a burst address RA2.sub.-- cd for the DR4 operation is internally generated by using an external address A2.sub.-- c for the DR4 operation, instead of using the address A1.sub.-- a for the DW2 operation as an initial burst address. In cycle C4, the write data W0d, W0c, W1a and W1b may be registered and they may not be written into memory cells until the DR4 operation has been completed.
Like cycle C2 with the burst write continue command, there is also no external address input in cycle C5 with a burst read continue command. In this cycle C5, subsequent internal burst address RA2.sub.-- ab is generated depending upon the external address A2.sub.-- c and the first read data R2c corresponding to the burst address RA2.sub.-- cd for the DR4 operation is driven to data bus. The reference symbol RA2.sub.-- cd (or RA2.sub.-- ab) of the burst address for the read data R2c and R2d (or R2a and R2b) represents that both of the data R2c and R2d (or R2a and R2b) are read out of the selected memory cells in parallel.
In cycle C6, a command SR1 representing an SDR burst read operation of burst length 1 (hereinafter abbreviated as "SRI operation") is given together with an external address A3.sub.-- d. In this single read cycle C6, the external address A3.sub.-- d itself becomes the internal address RA3.sub.-- d, without generating additional internal address, and the read data R2d and R2a corresponding to the DR4 operation appear on the data bus. As can be seen in FIG. 2, the prior art SRAM device 100 requires a single "no operation (NOP)" cycle without external address input when transitioning from a read cycle to a write cycle even though the NOP cycle is not required when switching from a write cycle to a read cycle. Thus, in cycle C7 of the clock signal CK, an NOP cycle is added for a next write operation which will be executed in subsequent cycle C8. In the NOP cycle C7, the final read data R2b corresponding to the DR4 operation is driven to the data bus without generating internal address and the DR4 operation is completed. Like the above-described burst write operations, the read data output sequence of the data R2c, R2d, R2a and R2b is also determined by both the external address A2.sub.-- c and the selected burst mode.
In cycle C8 of the clock signal CK, in which a command DW1 representing a DDR burst write operation with burst length of 1 is given together with an external address A4.sub.-- a, the write data W0d and W0c registered in cycle C4 are written into the memory cells selected by decoding internal address WA0.sub.-- dc.
As described above, the registered data W0d and W0c for the DW4 operation are written into memory cells in the write cycle C8 since the DR4 and SR1 operations have been completed. However, to write the registered data W0d and W0c into the memory cells designated by the internal address WA0.sub.-- cd in the first write cycle C8 after the SR1-operation, the memory device has difficulty in setting the burst address sequence counter fast with the internal address WA0.sub.-- dc because only a single burst address sequence counter 106 (shown in FIG. 1) is used for both read and write operations, resulting in address decoding speed loss.